System Level Formal Verification as a Service
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Alur R. “Formal verification of hybrid systems”. In: Proc. EMSOFT (2011), Taipei, Taiwan, 2011, pp. 273-278.
Mancini T., Mari F., Massini A., Melatti I., Merli F., Tronci E. “System level formal verification via model checking driven simulation”. In: Proc. CAV (2013), Saint Petersburg, Russia, 2013, pp. 296-312.
Mancini T., Mari F., Massini A., Melatti I., Tronci E. “Anytime system level verification via random exhaustive hardware in the loop simulation” . In: Proc. DSD (2014), Verona, Italy, 2014, pp. 236-245.
Mancini T., Mari F., Massini A., Melatti I., Tronci E.. “System level formal verification via distributed multi-core hardware in the loop simulation”. In: Proc. PDP (2014), Turin, Italy, 2014, pp. 734-742.
Penna G. Della, Intrigila B., Melatti I., Tronci E., Zilli. M. Venturini “Exploiting transition locality in automatic verification of finite state concurrent systems”. STTT, 2004; 6: 320–341.
Zuliani P., Platzer A., Clarke E.. “Bayesian statistical model checking with application to Simulink/Stateflow verification”. In: Proc. HSCC (2010), Stockholm, Sweden, 2010, pp. 243-252.
Mancini T., Mari F., Massini A., Melatti I., Tronci E. “SyLVaaS: System Level Formal Verification as a Service”. In: Proc. PDP (2015), Turku, Finland, 2015.
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(c) 2021 T. Mancini, F. Mari, A. Massini, I. Melatti, E. Tronci